A paper by Y. Sakai et al, entitled: "MOS Buried Load Logic," presented at the 1980 International Solid-State Circuits Conference of the IEEE, describes a technique for improving the integration density of a multi-cell MOS memory array, by configuring load devices for respective memory cells as vertical or buried JFET structures. According to the basic cell architecture described in this paper, and illustrated in the structural sectional view of FIG. 1 and the schematic view of FIG. 2, a portion of (a N-type) substrate 10 is masked in the course of formation of a (P-type) well 12 in which an (N)MOS device 14 is formed, so as to leave a `hole` 16 through the well and thereby form the channel of a vertical N-type (JFET) load device 17, which is intersected by a subsequently formed (N+) drain region 18 of the MOS device 14. With the load (the buried JFET) being `buried` within the same well region as the MOS cell, so that it does not occupy additional horizontal or surface semiconductor real estate on the memory chip, the integration density of the memory array is increased.
Unfortunately, because the pinch off voltage and cross-sectional dimensions of the vertical load JFET's channel region are determined by the processing conditions used to define the size of the `hole` 16 formed through the P well, repeatability among different memory chip lots is poor. In addition, since the entirety of the JFET channel coincides with the entirety of the hole through the well, the load JFET device consumes substantial power--a less than ideal property of a load device, which should serve to provide a high impedance and provide only a minimum leakage current that is just sufficient to maintain the storage node at its intended logic level.